It is known in the art to form dynamic semiconductor memory cells utilizing buried transistors and capacitors formed in trenches in a semiconductor substrate. Because such buried transistor-capacitor cells are compact, very large numbers of such cells can be accommodated on a single semiconductor chip, for example, 4 Mega-bits or more per chip. A typical prior art structure and method is described by A. H. Shah, "A 4-Mbit DRAM with Trench-Transistor Cell", IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October 1986, pages 618-626.
While prior art trench type transistor-capacitor cells have demonstrated the feasibility of forming very high bit count single chip semiconductor memories, such prior art cells and memories suffer from a number of limitations and disadvantages. For example, as the individual transistor-capacitor cells are moved closer and closer together to provide greater packing density and larger bit counts, it becomes more and more difficult to isolate the individual cells from each other. Further, the prior art structures and methods have undesirably high contact and line resistance which limits memory speed. Additionally, comparatively large diffused cell contact areas used in the prior art increase the susceptibility of the memory cells to soft bit errors.
These and other problems are overcome by the structure and method of the present invention. Accordingly, it is an object of the present invention to provide an improved structure and method for buried transistor-capacitor cells for semiconductor memories and other device functions.
It is a further object of the present invention to provide an improved cell having a smaller footprint than conventional cells so as to permit closer packing and higher bit counts in the same chip area.
It is an additional object of the present invention to provide an improved cell utilizing a buried MOSFET and capacitor wherein the material forming the channel region of the MOSFET is deposited separately from the remainder of the semiconductor substrate.
It is a further object of the present invention to provide an improved cell having low resistance contacts and intercell connections.
It is an additional object of the present invention to provide an improved cell wherein the buried transistor-capacitor structure is self-aligned.
For convenience of explanation, certain semiconductor regions are denoted as P or N in the structures and method illustrated herein. However, those of skill in the art will understand that this is merely for ease of explanation and not intended to be limiting, and that the invention being described includes arrangements where the conductivity types are inverted or where other combinations of P and N regions are used. The words trench and cavity are used interchangeably herein and are intended to refer to an opening extending from a principal surface of a semiconductor wafer or a semiconductor layer, part way through the thickness of the wafer or through the layer.